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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this produ ct without notice. copyright ? cirrus logic, inc. 2004 (all rights reserved) http://www.cirrus.com cs4351 192 khz stereo dac with 2 vrms line out features z multi-bit delta-sigma modulator z 24-bit conversion z up to 192 khz sample rates z 112 db dynamic range z -100 db thd+n z +3.3 v, +9 to 12 v, and vl power supplies z 2 vrms output into 5 k ? ac load z digital volume control with soft ramp ? 119 db attenuation ? 1/2 db step size ? zero crossing click-free transitions z atapi mixing z low clock jitter sensitivity z popguard technology ? for control of clicks and pops description the cs4351 is a complete stereo digital-to-analog sys- tem including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-em- phasis, volume control, chan nel mixing, analog filtering, and on-chip 2 vrms line level driver. the advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high toler- ance to clock jitter, and a minimal set of external components. these features are ideal for cost-sensitive, 2-channel audio systems including dvd players, a/v receivers, set-top boxes, digital tvs and vcrs, mini-component systems, and mixing consoles. ordering in formation cs4351-cz -10 to 70 c 20-pin tssop cs4351-czz, lead free -10 to 70 c 20-pin tssop CDB4351 evaluation board i pcm serial interface interpolation filter with volume control internal voltage reference external mute control dac serial audio input left and right mute controls 2 vrms line level right channel output 2 vrms line level left channel output reset 1.8 v to 3.3v dac register/hardware configuration level translator hardware or i 2 c/spi control data multibit ? modulator 3.3 v 9 v to 12 v interpolation filter with volume control amp + filter amp + filter auto speed mode detect multibit ? modulator sep ?04 ds566pp2
cs4351 2 ds566pp2 table 1. revision history release date changes a1 july 2003 initial release a2 august 2003 added i 2 c/spi switching characterics a3 november 2003 removed ?confidential?, moved legal statement to last page pp1 june 2004 updated legal. updated analog performance specifications (typ is improved). consolidated speed mode performance for analog performance. updated current consumption specificat ions (typ and min/max increased). updated psrr (improved typ performance for 60 hz). reduced recommended vbias+ capacitor in typical connection diagram (to improve startup settling times). changed bit 0 (popg) in register 07h to reserved (must always be 1). pp2 sep 2004 update w/ lead-free device ordering info.
cs4351 ds566pp2 3 table of contents 1. pin description ......................................................................................................... ........ 5 2. characteristics and specifications ........................................................................ 6 specified operating conditions . .............. ................ ............. ............. ............. ........... 6 absolute maximum ratings ...... ................ ................ ................ ............. ............. ........... 6 dac analog characteristics ....................................................................................... 7 combined interpolation & on-chip analog filter response .......................... 9 combined interpolation & on-chip analog filter response ........................ 10 switching specifications - serial audio interface .......................................... 11 switching characteristic s - control port - i 2 c format................................ 12 switching characteristics - control po rt - spi format ............................... 13 digital characteristics............................................................................................... 14 power and thermal characteristics .................................................................... 14 3. typical connection diagram ..................................................................................... 15 4. applications .............................................................................................................. ....... 16 4.1 sample rate range/operatio nal mode detect ................... ............................................ 16 4.1.1 auto-detect enabled ........................................................................................... 16 4.1.2 auto-detect disabled .......................................................................................... 16 4.2 system clocking ........................................................................................................... ... 17 4.3 digital interface format ... ............................................................................................... .18 4.3.1 stand-alone mode .............................................................................................. 18 4.3.2 control port mode .............................................................................................. 18 4.4 de-emphasis control ...................................................................................................... 1 9 4.4.1 stand-alone mode .............................................................................................. 19 4.4.2 control port mode ............................................................................................... 19 4.5 recommended power-up sequence ............... ................................................................ 20 4.5.1 stand-alone mode .............................................................................................. 20 4.5.2 control port mode ............................................................................................... 20 4.6 popguard ? transient control .......................................................................................... 21 4.6.1 power-up ............................................................................................................. 21 4.6.2 power-down ........................................................................................................ 21 4.6.3 discharge time ................................................................................................... 21 4.7 mute control .............................................................................................................. ...... 21 4.8 grounding and power supply arrangements .................................................................. 22 4.8.1 capacitor placement ..... ...................................................................................... 22 4.9 control port interface ...... .............................................................................................. .. 23 4.9.1 map auto increment ..... ...................................................................................... 23 4.9.2 i 2 c mode ............................................................................................................. 23 4.9.2.1 i 2 c write ............................................................................................. 23 4.9.2.2 i 2 c read ............................................................................................. 23 4.9.3 spi mode ............................................................................................................ 24 4.9.3.1 spi write ............................................................................................. 24 4.10 memory address po inter (map) ................................................................................ 26 5. register quick reference .......................................................................................... 26 6. register description .................................................................................................... 27 7. parameter definitions .................................................................................................. 34 8. package dimensions ..................................................................................................... 35 9. appendix ..... ................ ................. ................ ................ ................ ............. ............. ............ 36
cs4351 4 ds566pp2 list of figures figure 1. serial input timing .................................................................................................. ..... 11 figure 2. control port timing - i 2 c format ................................................................................. 12 figure 3. control port timing - spi format (write) ..................................................................... 13 figure 4. typical connection dia gram ........................................................................................ 15 figure 5. left justified up to 24-bit data ..... ................................................................................ 18 figure 6. i 2 s, up to 24-bit data ................................................................................................... 18 figure 7. right justified data ......................... ........................................................................ ..... 18 figure 8. de-emphasis curve ..... ............................................................................................... .19 figure 9. control port timing, i2c mode ........... .......................................................................... 24 figure 10. control port timing, spi mode .................................................................................... 25 figure 11. de-emphasis curve ................................................................................................... .. 28 figure 12. atapi block diagram ........................ ......................................................................... .29 figure 13. single speed (fast) stopband rejection ...................................................................... 36 figure 14. single speed (fast) transition band ............................................................................ 36 figure 15. single speed (fast) transition band (d etail) ................................................................ 36 figure 16. single speed (fast) passband ripple .... ...................................................................... 36 figure 17. single speed (slow) stopband rejection ..................................................................... 36 figure 18. single speed (slow) tr ansition band ........................................................................... 36 figure 19. single speed (slow) tr ansition band (detail) ............................................................... 37 figure 20. single speed (slow) passband ripple ......................................................................... 37 figure 21. double speed (fast) stopband rejectio n ..................................................................... 37 figure 22. double speed (fast) tr ansition band ........................................................................... 37 figure 23. double speed (fast) tr ansition band (detail) ............ ................................................... 37 figure 24. double speed (fast) passband ripple ......................................................................... 37 figure 25. double speed (slow) stopband rejection ................................................................... 38 figure 26. double speed (slow) transition band .......................................................................... 38 figure 27. double speed (slow) tr ansition band (detail) .............................................................. 38 figure 28. double speed (slow) pa ssband ripple ........................................................................ 38 figure 29. quad speed (fast) stopband rejection ....................................................................... 38 figure 30. quad speed (fast) transition band .... .......................................................................... 38 figure 31. quad speed (fast) tran sition band (detail) .................................................................. 39 figure 32. quad speed (fast) passband ripple .. .......................................................................... 39 figure 33. quad speed (slow) st opband rejection ...................................................................... 39 figure 34. quad speed (slow) transition band ............................................................................ 39 figure 35. quad speed (slow) tran sition band (detail) ................................................................ 39 figure 36. quad speed (slow) pa ssband ripple .......................................................................... 39
cs4351 ds566pp2 5 list of tables table 1. revision history ..................................................................................................... ..........2 table 2. cs4351 auto-detect .................................................................................................... ...16 table 3. cs4351 mode select .................................................................................................... ..16 table 4. single-speed mode stan dard frequencies ....................................................................17 table 5. double-speed mode stand ard frequencies...................................................................17 table 6. quad-speed mode stan dard frequencies .....................................................................17 table 7. digital interface format - stand-alone mode..................................................................18 table 8. digital interface form ats ............................................................................................. ....27 table 9. atapi decode .......................................................................................................... ......29 table 10. example digital volume settings ............ ......................................................................31
cs4351 6 ds566pp2 1. pin description pin name # pin description sdin 1 serial audio data input ( input ) - input for two?s complement serial audio data. sclk 2 serial clock ( input ) - serial clock for the serial audio interface. lrck 3 left / right clock ( input ) - determines which channel, left or ri ght, is currently active on the serial audio data line. mclk 4 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. vd 5 digital power ( input ) - positive power supply for the digital section. gnd 6 16 ground ( input ) - ground reference. rst 10 reset ( input ) - powers down device and resets all intern al resisters to their default settings when enabled. va 11 low voltage analog power ( input ) - positive power supply for the analog section. vbias 12 positive voltage reference ( output ) - positive reference voltage for the internal dac. vq 13 quiescent voltage ( output ) - filter connection for internal quiescent voltage. va_h 17 high voltage analog power ( input ) - positive power supply for the analog section. vl 20 serial audio interface power ( input ) - positive power for the serial audio interface bmutec amutec 14 19 mute control ( output ) - control signal for optional mute circuit. aoutb aouta 15 18 analog outputs ( output ) - the full scale analog line output level is specified in the analog characteris- tics table. control port definitions scl/cclk 7 serial control port clock ( input ) - serial clock for the control port interface. sda/cdin 8 serial control data ( input/output ) - input/output for i 2 c data. input for spi data. ad0/cs 9 address bit 0 / chip select ( input ) - chip address bit in i 2 c mode. control port enable in spi mode. stand-alone definitions dif0 dif1 8 7 digital interface format ( input ) - defines the required relationship between the left right clock, serial clock, and serial audio data. dem 9 de-emphasis ( input ) - selects the standard 15 s/50 s digital de-emphasis filter response for 44.1 khz sample rates sdin vl sclk amutec lrck aouta mclk va_h vd gnd gnd aoutb dif1(scl/cclk) bmutec dif0(sda/cdin) vq dem(ad0/cs ) vbias rst va 1 2 3 4 5 6 7 8 9 10 11 12 17 18 19 20 13 14 15 16
cs4351 ds566pp2 7 2. characteristics and specifications (min/max performance characteristics and specifications are guaranteed over the specified operating conditions. typical specifications are derived from performance measurements at t a = 25 c, va_h = 12 v, va = 3.3 v, vd = 3.3 v.) specified operating conditions (gnd = 0 v; all voltages with respect to ground.) absolute maximum ratings (gnd = 0 v; all voltages with respect to ground.) operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaran- teed at these extremes. parameters symbol min typ max units dc power supply high voltage analog power low voltage analog power digital power interface power v a_h v a v d v l 8.55 3.13 3.13 1.7 12 3.3 3.3 3.3 12.6 3.47 3.47 3.47 v v v v specified temperature range t a -10 - 70 c parameters symbol min max units dc power supply high voltage analog power low voltage analog power digital power interface power v a_h v a v d v l -0.3 -0.3 -0.3 -0.3 14 3.63 3.63 3.63 v v v v input current, any pin except supplies i in -10ma digital input voltage digital interface v in-l -0.3 v l + 0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c
cs4351 8 ds566pp2 dac analog characteristics (test conditions (unless otherwise specified): input test sig- nal is a 997 hz sine wave at 0 dbfs; measurement bandwidth 10 hz to 20 khz) notes: 1. one-half lsb of triangular pdf dither is added to data. analog characteristics (continued) parameter symbol min typ max unit all speed modes fs = 48, 96, and 192 khz dynamic range (note 2) 24-bit unweighted a-weighted 16-bit unweighted a-weighted 99 102 - - 109 112 95 98 - - - - db db db db total harmonic distortion + noise (note 2) 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - - -100 -89 -49 -92 -75 -35 -90 -79 -39 - - - db db db db db db all speed modes idle channel noise / signa l-to-noise ratio - 109 - db interchannel isolation (1 khz) - 100 - db parameters symbol min typ max units analog output - all modes full scale output voltage 1.9 2.0 2.1 vrms common mode voltage v q -4-vdc max dc current draw from an aout pin i outmax -10- a max current draw from vq i qmax -1- a interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c output impedance z out -50- ? ac-load resistance r l 5- -k ? load capacitance c l --100pf
cs4351 ds566pp2 9 combined interpolation & on-c hip analog filter response (the filter characteristics have been normalized to the sample ra te (fs) and can be referenced to the desired sample rate by multiplying the given characteristic by fs.) parameter fast roll-off unit min typ max combined digital and on-chip analog filt er response - single speed mode - 48 khz passband (note 3) to -0.01 db corner to -3 db corner 0 0 - - .454 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband 0.547 - - fs stopband attenuation (note 4) 102 - - db total group delay (fs = outp ut sample rate) - 9.4/fs - s intra-channel phase deviation - - 0.56/fs s inter-channel phase deviation - - 0 s de-emphasis error (note 5) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db combined digital and on-chip analog filt er response - double speed mode - 96 khz passband (note 3) to -0.01 db corner to -3 db corner 0 0 - - .430 .499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .583 - - fs stopband attenuation (note 4) 80 - - db total group delay (fs = outp ut sample rate) - 4.6/fs - s intra-channel phase deviation - - 0.03/fs s inter-channel phase deviation - - 0 s combined digital and on-chip analog filter response - quad speed mode - 192 khz passband (note 3) to -0.01 db corner to -3 db corner 0 0 - - .105 .490 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .635 - - fs stopband attenuation (note 4) 90 - - db total group delay (fs = outp ut sample rate) - 4.7/fs - s intra-channel phase deviation - - 0.01/fs s inter-channel phase deviation - - 0 s
cs4351 10 ds566pp2 combined interpolation & on-c hip analog filter response (cont.) notes: 2. slow roll-off interpolation filter is only available in control port mode. 3. response is clock dependent and will scale with fs. 4. for single speed mode, the measurement bandwidth is from stopband to 3 fs. for double speed mode, the measurement bandwidth is from stopband to 3 fs. for quad speed mode, the measurement bandwidth is from stopband to 1.34 fs. 5. de-emphasis is available only in single speed mode; only 44.1 khz de-emphasis is available in stand- alone mode. 6. amplitude vs. frequency plots of this data are available in ?appendix? on page 37. parameter slow roll-off (note 2) unit min typ max single speed mode - 48 khz passband (note 3) to -0.01 db corner to -3 db corner 0 0 - - 0.417 0.499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .583 - - fs stopband attenuation (note 4) 64 - - db total group delay (fs = outp ut sample rate) - 6.5/fs - s intra-channel phase deviation - - 0.14/fs s inter-channel phase deviation - - 0 s de-emphasis error (note 5) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db double speed mode - 96 khz passband (note 3) to -0.01 db corner to -3 db corner 0 0 - - .296 .499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .792 - - fs stopband attenuation (note 4) 70 - - db total group delay (fs = outp ut sample rate) - 3.9/fs - s intra-channel phase deviation - - 0.01/fs s inter-channel phase deviation - - 0 s quad speed mode - 192 khz passband (note 3) to -0.01 db corner to -3 db corner 0 0 - - .104 .481 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .868 - - fs stopband attenuation (note 4) 75 - - db group delay - 4.2/fs - s intra-channel phase deviation - 0.01/fs s inter-channel phase deviation - - 0 s
cs4351 ds566pp2 11 switching specifications - se rial audio interface parameters symbol min max units mclk frequency 1.024 51.2 mhz mclk duty cycle 45 55 % input sample rate (manual selection) single-speed mode double-speed mode quad-speed mode fs fs fs 4 50 100 50 100 200 khz khz khz input sample rate (auto selection) single-speed mode double-speed mode quad-speed mode fs fs fs 4 84 170 50 100 200 khz khz khz lrck duty cycle 40 60 % sclk pulse width low t sclkl 20 - ns sclk pulse width high t sclkh 20 - ns sclk period single speed mode t sclkw -- double speed mode t sclkw -- quad speed mode t sclkw -- sclk rising to lrck edge delay t slrd 20 - ns sclk rising to lrck edge setup time t slrs 20 - ns sdin valid to sclk rising setup time t sdlrs 20 - ns sclk rising to sdin hold time t sdh 20 - ns sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck figure 1. serial input timing 1 128 () fs --------------------- - 1 64 () fs ------------------ 2 mclk -----------------
cs4351 12 ds566pp2 switching characteristics - control port - i 2 c format (inputs: logic 0 = gnd, logic 1 = vl, c l =20pf) notes: 7. data must be held for sufficient time to brid ge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (p rior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 7) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rc -1s fall time scl and sda t fc , t fc -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t lo w t hdd t high t sud stop s tart sda scl t irs rst t hdst t rc t fc t sust t susp start stop repeated t rd t fd t ack figure 2. control port timing - i 2 c format
cs4351 ds566pp2 13 switching characteristics - co ntrol port - spi format (inputs: logic 0 = gnd, logic 1 = vl, c l =20pf) notes: 8. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 9. data must be held for sufficient time to bridge the transition time of cclk. 10. for f sck < 1 mhz. parameter symbol min max unit cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 8) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 9) t dh 15 - ns rise time of cclk and cdin (note 10) t r2 -100ns fall time of cclk and cdin (note 10) t f2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 3. control port timing - spi format (write)
cs4351 14 ds566pp2 digital characteristics power and thermal characteristics notes: 11. current consumption increases with increasing fs and increasing mclk. typ and max values are based on highest fs and highest mclk. va riance between speed modes is small. 12. i l measured with no external loading on pin 8 (sda). 13. power down mode is defined as res pin = low with all clock an d data lines held static. 14. valid with the recommended capacitor values on vq and v bias as shown in the typical connection diagram in section 3. parameters symbol min typ max units high-level input voltage vl = 3.3 v vl = 2.5 v vl = 1.8 v v ih v ih v ih 2.0 1.7 0.65?v l - - - - - - v v v low-level input voltage vl = 3.3 v vl = 2.5 v vl = 1.8 v v il v il v il - - - - - - 0.8 0.7 0.35?v l v v v input leakage current i in --10 a input capacitance - 8 - pf maximum mutec drive current - 2 - ma mutec high-level output voltage v oh -va_h- v mutec low-level output voltage v ol -0- v parameters symbol min typ max units power supplies power supply current n ormal operation, v a_h = 12 v (note 11) v a_h = 9 v v a = 3.3 v v d = 3.3 v interface current (note 12) v l = 3.3 v power-down state, all supplies (note 13) i a_h i a_h i a i d i l i pd - - - - - - 15 14 6 21 100 200 20 19 8 26 400 - ma ma ma ma a a power dissipation (all supplies) (note 11) va_h = 12 v normal operation power-down (note 13) va_h = 9 v normal operation power-down (note 13) - - - - 270 1 216 1 354 - 285 - mw mw mw mw power supply rejection ratio (note 14) (1 khz) (60 hz) psrr - - 60 60 - - db db
cs4351 ds566pp2 15 3. typical connection diagram 15 digital audio source vl gnd cs4351 mclk vd aouta 1 17 0.1 f + 10 f +3.3 v * c/ mode configuration 9 10 8 sdin 2 dif1(scl/cclk) dif0(sda/cdin) dem(ad0/cs) optional mute circuit rst bmutec 3.3 f aouta + + 12 13 vbias+ vq 7 4 3 lrck sclk 3.3 f 10 k ? 560 ? + 14 18 3.3 f 10k ? 560 ? + 15 aoutb 3.3 f va_h 0.1 f + 10 f gnd 6 0.1 f +1.8 v to vd +9 v to +12 v 5 20 amutec 19 va 11 0.1 f + 10 f +3.3 v 5.1 ?? 2.2 nf* 2.2 nf* *optional *shown value is for fc=130khz *remove this supply if optional resistor is present. the decoupling caps should remain. 576 k ? 412 k ? optional mute circuit aouta 576 k ? 412 k ? figure 4. typical connection diagram
cs4351 16 ds566pp2 4. applications 4.1 sample rate range/operational mode detect the device operates in one of thr ee operational modes. the allowed samp le rate range in each mode will depend on whether the auto-detect de feat bit is enabled/disabled. 4.1.1 auto-detect enabled the auto-detect feature is enabled by default. in this state, the cs4351 will auto-detect the correct mode when the input sample rate (f s ), defined by the lrck frequenc y, falls within one of the rang- es illustrated in table 2. sample rates outside the specified range for each mode are not supported. 4.1.2 auto-detect disabled the auto-detect feature can be de feated only by the format bits in the control port register 02h. in this state, the cs4351 will not auto-detect the correct mode ba sed on the input sample rate (f s ). the operational mode must then be se t manually according to one of th e ranges illustrated in table 3. please refer to section 6.2.3 for implementation details. sample rates outside the specified range for each mode are not supported. in stand-alone mode it is not possible to di sable auto-detect of sample rates. input sample rate (f s )mode 4 khz - 50 khz single speed mode 84 khz - 100 khz double speed mode 170 khz - 200 khz quad speed mode table 2. cs4351 auto-detect fm1 fm0 input sample rate (f s )mode 0 0 auto speed mode detect auto 0 1 4 khz - 50 khz single speed mode 1 0 50 khz - 100 khz double speed mode 1 1 100 khz - 200 khz quad speed mode table 3. cs4351 mode select
cs4351 ds566pp2 17 4.2 system clocking the device requires external gene ration of the master (mclk), left /right (lrck) and serial (sclk) clocks. the left/right clock, defined also as the input sample rate (f s ), must be synchronously derived from the mclk according to specified ratio s. the specified ratios of mclk to lrck, along with several stan- dard audio sample rates and the required mclk frequency, are illustr ated in tables 4-6. refer to section 4.3 for the required sclk timing associated with the se lected digital interface format, and switching specifications - serial audio interface, page 11 for the maximum allowed clock frequencies. sample rate (khz) mclk (mhz) 256x 384x 512x 768x 1024x 1152x 32 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 table 4. single-speed mode standard frequencies sample rate (khz) mclk (mhz) 128x 192x 256x 384x 512x 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 table 5. double-speed mode standard frequencies sample rate (khz) mclk (mhz) 64x 96x 128x 192x 256x 176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520 table 6. quad-speed mode standard frequencies = denotes clock modes which are not auto detected
cs4351 18 ds566pp2 4.3 digital interface format the device will accept audio samples in 1 of 4 digital interface formats in stand-alone mode , as illustrated in table 7, and 1 of 6 formats in contro l port mode, as illustrated in table 8. 4.3.1 stand-alone mode the desired format is selected via the dif1 and di f0 pins. for an illustration of the required rela- tionship between the lrck, sclk and sdin, see figures 5-7. for a ll formats, sdin is valid on the rising edge of sclk. also, sclk must have at least 32 cycles per l rck period in format 2, and 48 cycles per lrck period in format 3. 4.3.2 control port mode the desired format is sel ected via the dif2, dif1 and dif0 bits in the mode cont rol 2 register (see section 6.2.1) . for an illustrati on of the required relationship between lrck, sclk and sdin, see figures 5-7. for all formats, sdin is valid on the rising edge of sclk. also, sclk must have at least 32 cycles per lrck period in format 2, 48 cycles in format 3, 40 cycles in format 4, and 36 cycles in format 5. dif0 dif1 description format figure 00 i 2 s, up to 24-bit data 06 01 left justified, up to 24-bit data 15 10 right justified, 24-bit data 27 11 right justified, 16-bit data 37 table 7. digital interface format - stand-alone mode lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 lsb msb lsb figure 5. left justified up to 24-bit data lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb lsb figure 6. i 2 s, up to 24-bit data lrck sclk left channel sdin -6 -5 -4 -3 -2 -1 -7 +1 +2 +3 +4 +5 msb right channel lsb msb +1 +2 +3 +4 +5 lsb -6 -5 -4 -3 -2 -1 -7 msb figure 7. right justified data
cs4351 ds566pp2 19 4.4 de-emphasis control the device includes on-chip digi tal de-emphasis. figure 8 show s the de-emphasis curve for f s equal to 44.1 khz. the frequency response of the de-emphasis cu rve will scale proportiona lly with changes in sam- ple rate, fs. notes: de-emphasis is only av ailable in single-speed mode. 4.4.1 stand-alone mode when pulled to vl the dem pin activates the 44.1 khz de-emphasi s filter. when pulled to gnd the dem pin turns off the de-emphasis filter. 4.4.2 control port mode the mode control bits selects either the 32, 44.1, or 48 khz de-emphasis filter. please see section 6.2.2 for the desired de-emphasis control. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 8. de-emphasis curve
cs4351 20 ds566pp2 4.5 recommended power-up sequence 4.5.1 stand-alone mode 1. hold rst low until the power supplies and configurat ion pins are stable, and the master and left/right clocks are locked to th e appropriate frequencies, as disc ussed in section 4.2. in this state, the control port is reset to its default settings, vq will remain low, a nd vbias will be connected to va. 2. bring rst high. the device will remain in a low power state with vq low and will initiate the stand-alone power-up se quence after approximately 512 lrck cycles in single-speed mode (1024 lrck cycles in double-speed mode, a nd 2048 lrck cycles in quad-speed mode). 4.5.2 control port mode 1. hold rst low until the power supply is st able, and the master and left /right clocks are locked to the appropriate frequencies, as disc ussed in section 4.2. in this state, the contro l port is reset to its default settings, vq will remain low, and vbias will be connected to va. 2. bring rst high. the device will remain in a low power state with vq low. 3. perform a control port write to the cp_en bi t prior to the completion of approximately 512 lrck cycles in single-speed mode (1024 lrck cycles in double-speed mode, and 2048 lrck cycles in quad-speed mode). the desired register settings can be loaded while keeping the pdn bit set to 1. 4. set the pdn bit to 0. this will initiate the power-up sequence, which lasts approximately 50 s when the popg bit is set to 0. if the popg bit is set to 1, see section 4.6 for a complete description of power-up timing.
cs4351 ds566pp2 21 4.6 popguard ? transient control the cs4351 uses a novel technique to minimize the effects of output tr ansients during power-up and pow- er-down. this technology, when used with external dc-blocking capacitors in series with the audio out- puts, minimizes the audio transients commonly produ ced by single-ended single- supply converters. it is activated inside the dac when the rst pin is toggled and re quires no other external control, aside from choosing the appropriate dc-blocking capacitors. 4.6.1 power-up when the device is initially powered-up, the audio outputs, a outa and aoutb, are clamped to gnd. following a delay of approxi mately 1000 sample periods, each output begins to ramp toward the quiescent voltage. approximately 10,000 lr ck cycles later, the outputs reach v q and audio output begins. this gradual voltage ramping allows time for the external dc-blocking capacitors to charge to the quiescent voltage, minimizing audible power-up transients. 4.6.2 power-down to prevent audible transients at power-down, the device must fi rst enter its power-down state. when this occurs, audio output ceases and the inte rnal output buffers ar e disconnected from aou- ta and aoutb. in their place, a soft-start curren t sink is substituted which allows the dc-block- ing capacitors to slowly discharge. once this ch arge is dissipated, the pow er to the device may be turned off and the system is ready for the next power-on. 4.6.3 discharge time to prevent an audio transient at the next power-on, the dc-block ing capacitors must fully dis- charge before turning on the power or exiting the power-down state. if full discharge does not oc- cur, a transient will occur when the audio outputs are initially cl amped to gnd. the time that the device must remain in the power- down state is related to the valu e of the dc-blocking capacitance and the output load. for example, with a 3.3 f capacitor, the mi nimum power-down time will be approximately 0.4 seconds. 4.7 mute control the mute control pins go active dur ing power-up initialization, reset, mu ting (see section 6.4.3), or if the mclk to lrck ratio is incorrect. th ese pins are intended to be used as control for external mute circuits to prevent the clicks and pops that can occu r in any single-ended single supply system. use of the mute control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. also, use of the mute control function can enable the system de- signer to achieve idle channel noise/s ignal-to-noise ratios which are onl y limited by the external mute cir- cuit. please see ?typical connection diagram? on page 15 for a sugge sted mute circuit for single supply systems. this fet circuit must be placed in series after the rc filt er, otherwise noise may occur during muting conditions. further es d protection will need to be taken in to consideration fo r the fet used. if dual supplies are available, the bjt mute circuit fr om figure 12 in the cs4398 da tasheet (active low) may be used.
cs4351 22 ds566pp2 4.8 grounding and power supply arrangements as with any high resolution converter, the cs4351 re quires careful attention to power supply and ground- ing arrangements if its potential pe rformance is to be realized. figu re 4 shows the recommended power arrangements, with va_h, va, vd, and vl connected to clean supplie s. if the ground planes are split between digital ground and analog ground, the gnd pins of the cs4351 should be connected to the analog ground plane. all signals, especially cloc ks, should be kept away from the vbias and vq pins in order to avoid unwant- ed coupling into the dac. 4.8.1 capacitor placement decoupling capacitors should be place d as close to the dac as possi ble, with the low value ceram- ic capacitor being the closest. to further minimize impedance, th ese capacitors should be located on the same layer as the dac. if desired, all supp ly pins may be connected to the same supply, but a decoupling capacitor should sti ll be placed on each supply pin. notes: all decoupling capacitors should be referenced to analog ground. the CDB4351 evaluation board demonstrates the optimum layout and power supply arrangements.
cs4351 ds566pp2 23 4.9 control port interface the control port is used to load all the internal register settings (see section 6). the operation of the control port may be completely asynchronous with the audio sample rate. howeve r, to avoid potential interference problems, the control port pins should re main static if no operation is required. the control port operates in one of two modes: i 2 c or spi. 4.9.1 map auto increment the device has map (memory addr ess pointer) auto increment capa bility enabled by the incr bit (also the msb) of the map. if incr is set to 0, map will stay constant for successive i 2 c writes or reads and spi writes. if incr is set to 1, map will auto increment after each byte is written, allowing block reads or writ es of successive registers. 4.9.2 i 2 c mode in the i 2 c mode, data is clocked into and out of the bi -directional serial cont rol data line, sda, by the serial control port clock, scl (see figure 9 for the clock to da ta relationship). there is no cs pin. pin ad0 enables the user to a lter the chip addr ess (100110[ad0][r/w ]) and should be tied to vl or gnd as required, before powering up the device. if the de vice ever detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. 4.9.2.1 i 2 c write to write to the device, follow the procedure be low while adhering to the control port switching specifications in section 7. 1) initiate a start condition to the i 2 c bus followed by the addr ess byte. the upper 6 bits must be 100110. the seventh bit mu st match the setting of the ad0 pin, and the eighth must be 0. the eighth bit of the address byte is the r/w bit. 2) wait for an acknowledge (ack) from the part, then writ e to the memory address pointer, map. this byte points to th e register to be written. 3) wait for an acknowledge (ack) from the part, then write the desired data to the register pointed to by the map. 4) if the incr bit (see section 4.9.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a stop condition to the bus. 5) if the incr bit is set to 0 and further i 2 c writes to other registers are desired, it is necessary to initiate a repeated start c ondition and follow the procedure detailed fro m step 1. if no fur- ther writes to other registers are desi red, initiate a stop condition to the bus. 4.9.2.2 i 2 c read to read from the device, follow the procedure be low while adhering to the control port switch- ing specifications.
cs4351 24 ds566pp2 1) initiate a start condition to the i 2 c bus followed by the addr ess byte. the upper 6 bits must be 100110. the seventh bit mu st match the setting of the ad0 pin, and the eighth must be 1. the eighth bit of the address byte is the r/w bit. 2) after transmitting an acknowle dge (ack), the device will then transmit the contents of the register pointed to by th e map. the map register will contain the addres s of the last register written to the map, or the default address (see section 4.10.2) if an i 2 c read is the first opera- tion performed on the device. 3) once the device has transmit ted the contents of the register pointed to by the map, issue an ack. 4) if the incr bit is set to 1, the device will continue to transmit th e contents of successive registers. continue providing a cl ock and issue an ack after each byte until all the desired reg- isters are read, then initiate a stop condition to the bus. 5) if the incr bit is set to 0 and further i 2 c reads from other registers are desired, it is necessary to initiate a repeated start condition and foll ow the procedure detailed from steps 1 and 2 from the i 2 c write instructions followed by step 1 of the i 2 c read section. if no further reads from other registers are de sired, initiate a stop condition to the bus. 4.9.3 spi mode in spi mode, data is cloc ked into the serial contro l data line, cdin, by the serial control port clock, cclk (see figure 10 for the cl ock to data rela tionship). there is no ad0 pin. pin cs is the chip select signal and is used to control spi writes to the control port. when the device detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. all signals are inputs and data is clocked in on the rising edge of cclk. 4.9.3.1 spi write to write to the device, follow the procedure be low while adhering to the control port switching specifications in section 7. 1) bring cs low. 2) the address byte on the cdin pin must then be 10011000. 3) write to the memory address pointer, map. this byte points to the register to be written. sda scl 100110 ad0 r/w start ack data 1-8 ack data 1-8 ack stop note note: if operation is a write, this byte contains the memory address pointer, map. if operation is a read, this byte contains the data of the register pointed to by the map. figure 9. control port timing, i 2 c mode
cs4351 ds566pp2 25 4) write the desired data to th e register pointed to by the map. 5) if the incr bit (see section 4.9.1) is set to 1, repeat the previous step until all the desired registers are written, then bring cs high. 6) if the incr bit is set to 0 and further spi wr ites to other registers are desired, it is necessary to bring cs high, and follow the procedure detailed fr om step 1. if no further writes to other registers are desired, bring cs high. map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 1001100 figure 10. control port timing, spi mode
cs4351 26 ds566pp2 4.10 memory address pointer (map) 4.10.1 incr (auto map increment enable) default = ?0? 0 - disabled 1 - enabled 4.10.2 map (memory address pointer) default = ?0000? 76543210 incr reserved reserved reserved map3 map2 map1 map0 00000000
cs4351 ds566pp2 27 5. register quick reference addr function 7 6 5 4 3 2 1 0 1h chip id part4 part3 part2 part1 part0 rev2 rev1 rev0 default 11 1 1 1--- 2h mode control reserved dif2 dif1 dif0 dem1 dem0 fm1 fm0 default 00 0 00000 3h volume, mixing, and inversion control volb=a inverta invertb reserved atapi3 atapi2 atapi1 atapi0 default 000 0 1 001 4h mute control amute reserved mutec a=b mute_a mute_b reserved reserved reserved default 100 0 0 000 5h channel a volume control vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 default 000 0 0 000 6h channel b volume control vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 default 000 0 0 000 7h ramp and filter control szc1 szc0 rmp_up rmp_dn reserved filt_sel reserved reserved default 101 1 0 001 8h misc. control pdn cpen freeze reserved reserved reserved reserved reserved default 100 0 0 000
cs4351 28 ds566pp2 6. register description ** all register access is r/w unless specified otherwise** 6.1 chip id - register 01h function: this register is read-only. bits 7 through 3 are t he part number id which is 11111b and the remaining bits (2 through 0) are for the chip revision (rev. a = 000, rev. b = 001, ...) 6.2 mode control 1 - register 02h 6.2.1 digital interface format (dif2:0) bits 6-4 function: these bits select the interface fo rmat for the serial audio input. the required relationship between the left/right clock, se rial clock and serial data is defined by the digital interface format and the options are detailed in figures 5-7. 76543210 part4 part3 part2 part1 part0 rev2 rev1 rev0 11 1 11 - - - 76543210 reserved dif2 dif1 dif0 dem1 dem0 fm1 fm0 00 0 00000 dif2 dif1 dif0 description format figure 000 left justified, up to 24-bit data 0 (default) 5 001 i 2 s, up to 24-bit data 16 010 right justified, 16-bit data 27 011 right justified, 24-bit data 37 100 right justified, 20-bit data 47 101 right justified, 18-bit data 57 110 reserved 111 reserved table 8. digital interface formats
cs4351 ds566pp2 29 6.2.2 de-emphasis control (dem1:0) bits 3-2 . default = 0 00 - no de-emphasis 01 - 44.1 khz de-emphasis 10 - 48 khz de-emphasis 11 - 32 khz de-emphasis function: selects the appropriate digital filter to maintain the stan- dard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 khz sample rates. (see figure 11) note: de-emphasis is only available in single speed mode 6.2.3 functional mode (fm) bits 1-0 default = 00 00 - auto speed mode detect 01 - single-speed mode (4 to 50 khz sample rates) 10 - double-speed mode (50 to 100 khz sample rates) 11 - quad-speed mode (100 to 200 khz sample rates) function: selects the required range of input sample rates or dsd mode. 6.3 volume mixing and invers ion control - register 03h 6.3.1 channel a volume = channel b volume (volb=a) bit 7 function: when set to 0 (default) the aouta and aoutb volume levels are independently controlled by the a and the b channel volume control bytes. when set to 1 the volume on both aouta and aoutb are determined by the a channel attenuation and volume control bytes, and the b channel bytes are ignored. 6.3.2 invert signal polarity (invert_a) bit 6 function: when set to 1, this bit inverts the signal polarity of channel a. when set to 0 (default), this function is disabled. b7 b6 b5 b4 b3 b2 b1 b0 volb=a invert a invert b reserved atapi3 atapi2 atapi1 atapi0 00001001 figure 11. de-emphasis curve gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz
cs4351 30 ds566pp2 6.3.3 invert signal polarity (invert_b) bit 5 function: when set to 1, this bit inverts the signal polarity of channel b. when set to 0 (default), this function is disabled. 6.3.4 atapi channel mixing and muting (atapi3:0) bits 3-0 default = 1001 - aouta=al, aoutb=br (stereo) function: the cs4351 implements the channel mixing functions of the atapi cd-rom specification. refer to ta- ble 9 and figure 12 for additional information. atapi3 atapi2 atapi1 atapi0 aouta aoutb 0 0 0 0 mute mute 0001 mute br 0010 mute bl 0 0 1 1 mute b[(l+r)/2] 0100 ar mute 0101 ar br 0110 ar bl 0111 ar b[(l+r)/2] 1000 al mute 1001 al br 1010 al bl 1011 al b[(l+r)/2] 1 1 0 0 a[(l+r)/2] mute 1 1 0 1 a[(l+r)/2] br 1 1 1 0 a[(l+r)/2] bl 1 1 1 1 a[(l+r)/2] b[(l+r)/2] table 9. atapi decode ? a channel volume control aouta aoutb left channel audio data right channel audio data b channel volume control mute mute figure 12. atapi block diagram
cs4351 ds566pp2 31 6.4 mute control - register 04h 6.4.1 auto-mute (amute) bit 7 function: when set to 1 (default) the digital -to-analog converter output will mute following the reception of 8192 consecutive audio samples of static 0 or -1. a si ngle sample of non-static data will release the mute. detection and muting is done independently for ea ch channel. the quiescent voltage on the output will be retained and the mute control pi n will go active during the mute period. when set to 0 this function is disabled 6.4.2 amutec = bmutec (mutec a=b) bit 5 function: when set to 0 (default) the amutec and bmutec pins operate independently. when set to 1, the individual controls for amut ec and bmutec are internally connected through an and gate prior to the output pins. th erefore, the external amutec a nd bmutec pins will go active only when the requirements for both amutec and bmutec are valid. 6.4.3 a channel mute (mute_a) bit 4 b channel mute (mute_b) bit 3 function: when set to 1, the digital-to-anal og converter output will mute. the quiescent vo ltage on the output will be retained. the muting function is effected, simila r to attenuation changes, by the soft and zero cross bits in the volume and mixing c ontrol register. the co rresponding mutec pin will go active following any ramping due to the soft and zero cross function. when set to 0 (default) this function is disabled. 76543210 amute reserved mutec a=b mute_a mute_b reserved reserved reserved 10000000
cs4351 32 ds566pp2 6.5 channel a volume control - register 05h channel b volume control - register 06h 6.5.1 digital volume control (vol7:0) bits 7-0 default = 00h (0 db) function: the digital volume control registers allow independent control of the si gnal levels in 1/2 db increments from 0 to -127.5 db. volume settings are decoded as shown in table 10. the volume changes are im- plemented as dictated by the soft and zero cro ss bits in the power and muting control register. the actual attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12. 6.6 ramp and filter c ontrol - register 07h 6.6.1 soft ramp and zero cross control (szc1:0) bits 7-6 default = 10 function: immediate change when immediate change is select ed all level changes will take ef fect immediately in one step. zero cross zero cross enable dictates that si gnal level changes, either by atte nuation changes or muting, will occur on a signal zero crossing to mini mize audible artifacts. the requeste d level change will occur after a time- out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal 76543210 vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 00000000 binary code decimal value volume setting 00000000 0 0 db 00000001 1 -0.5 db 00000110 6 -3.0 db 11111111 255 -127.5 db table 10. example digital volume settings 76543210 szc1 szc0 rmp_up rmp_dn reserved filt_sel reserved reserved 10110001 szc1 szc0 description 0 0 immediate change 01 zero cross 10 soft ramp 1 1 soft ramp on zero crossings
cs4351 ds566pp2 33 does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. soft ramp pcm soft ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the ne w level at a rate of 1 db per 8 left/right clock periods. soft ramp and zero cross soft ramp and zero cross enable dictate that signal level changes, either by attenuation changes or mut- ing, will occur in 1/8 db steps and be implemented on a sign al zero crossing. the 1/8 db level change will occur after a time-out period between 512 and 1024 sa mple periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. 6.6.2 soft volume ramp-up after error (rmp_up) bit 5 function: when set to 1 (default), an un-mu te will be performed after executi ng a filter mode change, after a lrck/mclk ratio change or error, and after changing the functional mode. this un-mute is affected, similar to attenuation changes, by the soft and zero cr oss bits in the volume and mixing control register. when set to 0, an immediate un-mute is performed in these instances. note: for best results, it is recommended that th is feature be used in conjunction with the rmp_dn bit. 6.6.3 soft ramp-down before filter mode change (rmp_dn) bit 4 function: when set to 1 (default), a mute will be performed prior to executing a f ilter mode change. this mute is affected, similar to attenuation changes, by the soft and zero cross bits in the volume and mixing control register. when set to 0, an immediate mute is performed prior to executing a filter mode change. note: for best results, it is recommended that this feature be used in conjunction with the rmp_up bit. 6.6.4 interpolation filter select (filt_sel) bit 2 function: when set to 0 (default), the interp olation filter has a fast roll off. when set to 1, the interpolat ion filter has a slow roll off. the specifications for each filter can be found in th e ?combined interpolation & on-chip analog filter re- sponse? on page 9, and response plots can be found in figures 15 to 36.
cs4351 34 ds566pp2 6.7 misc control - register 08h 6.7.1 power down (pdn) bit 7 function: when set to 1 (default) the entire device will enter a low-power state an d the contents of the control reg- isters will be retained. the power-down bit defaults to ?1? on power-up and must be disabled before normal operation in control port mode can occur. this bit is ignored if cpen is not set. 6.7.2 control port enable (cpen) bit 6 function: this bit is set to 0 by default, allowing the device to power-up in stand-alone mode. control port mode can be accessed by setting this bit to 1. this will allo w operation of the device to be controlled by the reg- isters and the pin definitions will conform to cont rol port mode. 6.7.3 freeze controls (freeze) bit 5 function: when set to 1, this function allows modifications to be made to the registers without the changes taking effect until freeze is set back to 0. to make multiple changes in th e control port registers take effect simultaneously, enable the freeze bit, make al l register changes, then disable the freeze bit. when set to 0 (default), register changes take effect immediately. 76543210 pdn cpen freeze reserved reserved reserved reserved reserved 10000000
cs4351 ds566pp2 35 7. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to- noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distor tion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries asso ciation of japan , eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right cha nnels. measured for each channel at the converter's output with all zeros to the input under test and a fu ll-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c. intra-channel phase deviation the deviation from linear phase within a given channel. inter-channel phase deviation the difference in phase between channels.
cs4351 36 ds566pp2 8. package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion /intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximu m material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.252 0.256 0.259 6.40 6.50 6.60 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- -- 0.026 -- -- 0.65 l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 20l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view parameters symbol min typ max units package thermal resistance 20l tssop ja -72-c/watt
cs4351 ds566pp2 37 9. appendix 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 13. single speed (fast) stopband reject ion figure 14. single speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 15. single speed (f ast) transition band (detail) figure 16. single speed (fast) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 17. single speed (slow) stopband rejection figure 18. single speed (slow) transition band
cs4351 38 ds566pp2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) figure 19. single speed (slow) transition band (detail) figure 20. single speed (slow) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 21. double speed (fast) stopband rejection figure 22. double speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 23. d ouble speed (fast) tran sition band (detail) figure 24. double speed (fast) passband ripple
cs4351 ds566pp2 39 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 25. double speed (slow) stopband rejection figure 26. double speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 27. double speed (slow) transition band (d etail) figure 28. double speed (slow) passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 29. quad speed (fast) stopband rejection figure 30. quad speed (fast) transition band
cs4351 40 ds566pp2 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 31. quad speed (fast) transition band (d etail) figure 32. quad speed (fast) passband ripple 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 33. quad speed (slow) stopband rejection figure 34. quad speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 35. quad speed (slow) transition band (detail) figure 36. quad speed (slow) passband ripple
cs4351 ds566pp2 41 contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find one nearest you go to www.cirrus.com important notice "preliminary" product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the l atest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to th e terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by fu rnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other inte llectual property rights. cirrus owns the copyrights associated with the information contained here- in and gives consent for copies to be made of the information only for use within your organization with respect to cirrus inte grated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purp oses, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("critical applications"). cirrus products are not designed, authorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, life support products or other critical applications (including medical devices, aircraft systems or components and pers onal or automotive safety or security devices). inclusion of cirrus products in such applications is understood to be fully at the custom- er's risk and cirrus disclaims and makes no warranty, express, statut ory or implied, including the implied warranties of merchantability and fitness for pa rticular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer's cus tomer uses or permits the u se of cirrus products in crit ical applicat ions, customer agrees, by such use, to fully indemnify cirrus, its of ficers, directors, employees, di stributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, the cirrus logic logo designs, and popguard are trademarks of cirrus logic, inc. all other brand and prod uct names in this document may be trademarks or service marks of their respective owners. i 2 c is a registered trademark of philips semiconductor. purchase of i 2 c components of cirrus logic, inc., or one of its sublicensed associated companies conveys a license under the philips i 2 c patent rights to use those components in a standard i 2 c system.

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